028-61682666
Responsibilities:
1. Be engaged in layout and verification of simulation layout;
2. Responsible for module maintenance and upgrade;
3. Complete back-end physical verification, including DRC, LVS, LPE parameter extraction.
Requirements:
1. Bachelor degree or above, major in electronics, at least 2 years related working experience;
2. Proficient in using vituoso layout tools and calibre physical verification tools;
3. Familiar with semiconductor technology and process;
4. Experience in io layout design, familiar with the solutions of latch up, ESD and antenna effect in layout design;
5. 55 nm and more advanced technology experience is preferred; PLL layout design experience is preferred; high speed layout design experience is preferred;
6. Good at communication, strong sense of responsibility, good at team work.
If you are interested, please send your resume to: hr@anlogcircuit.cn
Contact: 028-61682666-804
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